1. Field of the Invention
The present invention relates to a semiconductor layout structure, and more particularly, to a semiconductor layout structure capable of adapting to multiple patterning technique in back-end-of-line (hereinafter abbreviated as BEOL) processing.
2. Description of the Prior Art
Fabrication of microstructures in semiconductor integrated circuits (hereinafter abbreviated as ICs) requires tiny elements of precisely controlled size formed in a material layer of an appropriate substrate such as semiconductor substrate/layers, dielectric layers and/or metal layers. These tiny elements are generated by patterning the abovementioned substrate/layers, for instance, by performing photolithography and etching processes. For this purposes, in conventional semiconductor techniques, a mask layer is formed on the material substrate/layers, and these tiny elements are defined in the mask layer and followed by being transferred to the objective material substrate/layers. Generally, the mask layer may include or is formed by means of a layer of photoresist that is patterned by lithographic process and/or patterned hard mask including the patterns transferred from the patterned photoresist. Since the dimensions of the patterns in sophisticated ICs are steadily decreasing, the equipment used for patterning devices features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is taken as a measure specifying the consistent ability to print minimum images under conditions of predefined manufacturing variations.
As feature sizes are decreased under 85 nanometers (hereinafter abbreviated as nm), the existing single patterning process has met its bottleneck to successfully produce the features. In order to push the lithographic limit further and to create even smaller, more densely packed devices, multiple patterning technology such as double patterning process, are being developed with presently available manufacturing equipment. Conventional multiple patterning process includes a litho-etching-litho-etching (hereinafter abbreviated as LELE) process, a litho-freeze-litho-etch (hereinafter abbreviated as LFLE) process, double patterning process, and a self-aligned double patterning (hereinafter abbreviated as SADP) process (also known as a spacer image transfer (hereinafter abbreviated as SIT) process).
Typically, the multiple patterning process is to decompose dense layout patterns into sub-patterns and then use two or more masks to print each sub-pattern. By transferring the sub-patterns to the photoresist layer/mask layer, the wanted patterns are re-constructed and obtained. It is found that the multiple patterning process gives rise to process control challenges. Thus, process complexity and process cost are unavoidably increased with the involvement of the multiple patterning process.